In the packaging of electronic devices, through a series of interfaces, conductors are progressively increased in spacing for ease and reliability in external connection. As dimensions become smaller, it becomes advantageous to be able to mount conductors on more than one level of a carrier and to be able to join them at an interface with corresponding connection locations on an essentially single level surface of a substrate. The substrate may be a semiconductor integrated circuit with connection locations on the surface thereof or a wiring module such as a buried conductor multilevel ceramic or dielectric laminate that provides further interconnection to device terminals. The carrier is generally a flexible dielectric film on which there is essentially a fan-out pattern of conductors with the closer spaced end of each conductor extending beyond an edge of the dielectric film for bonding to a location on the substrate.
With continued downsizing, as the art requires greater packing densities, conductors are being placed on both sides of the carrier film. This introduces a new problem in the fact that the conductor ends are at different levels with respect to the surface of the substrate. The problem has received some attention in the art. In Japanese 63-221635(A), conductors on different sides of carrier films are bent to a common level on a substrate. In Japanese 63-252453(A), small interconnecting wires are used in bonding connections from conductors at different levels on a carrier to closely spaced pads on the substrate surface. In Japanese 55-115339(A), the carrier has offset edges for conductor arrays that are at different levels and small interconnecting wires are used to go from the different levels to the pads on the substrate surface. The solutions heretofore in the art, however, require either a conductor shaping operation or the bonding of wire members which can result in fatigue or bonding failures.